At Computex 2019 during AMD's keynote, AMD CEO Dr. Lisa Su unveiled details new X570 chipset designed for the upcoming Ryzen 3000 series "Matisse" processors. The new 3rd generation of AM4 motherboards include PCIe 4.0 support, native USB 3.1 Gen2 ports, and a slightly more power hungry TDP, which means most motherboard manufacturers are likely to use actively cooled chipset heatsinks.

The new X570 chipset marks the first consumer motherboard chipset to feature PCIe 4.0 by default. We saw that manufacturers were preparing its previous generation X470/B450 motherboards to offer limited PCIe 4.0 support through a wave of firmware updates – taking advantage of the CPU's independent on-die PCIe controller – but due to certain requirements of PCIe 4.0, it's likely that previous generation boards will only have the top full-length slot running PCIe 4.0 when paired with a Ryzen 3000 series processor. The limitations are due to the length of the traces that the PCIe 4.0 interface requires. This means traces longer than a few inches won't be able to operate PCIe 4.0 unless the traces are fitted with redrivers to push the signal further down the board.

The MSI MEG X570 Godlike motherboard

With the new X570 boards, the implementation of PCIe 4.0 has been thought of from the get-go, with motherboards optimized for the interface with most models likely featuring redrivers on the furthest away slots. When paired with a Ryzen 3000 series processor, for a typical X570 motherboard what we'll see is that the lanes going into the top PCIe slot will come directly from the processor itself, as will the four PCIe lanes assigned to the first NVMe M.2 slot. This means that the X570 chipset – which also supports PCIe 4.0, but is not a requirement for the CPU-hosted lanes to use PCIe 4.0 – can use its own lanes for USB 3.1 Gen2 capability. Not only this, but it also allows the chipset to handle Wi-Fi, Bluetooth, and SATA responsibilities.

One of the caveats to a more powerful chipset is that it draws around 11 W of power; for comparative reasons, the X470 chipset drew around 6 W of power to operate. (This is different to the 15W being reported - it appears AMD is making two variants of the chipset, with the 11W on consumer boards and the 15W for enterprise, with the 15W having more PCIe lanes.)

Another change to the way AMD develops its chipsets is that everything is now done in-house, licensing IP from ASMedia and others, instead of completely outsourcing its chipset design to ASMedia as it did with X470 and X370. The main reasons for the TDP increase are due to PCIe 4.0. Speaking to AMD's partners, we expect a series of updates thick and fast to add additional power management features to the chipset between now and the CPU launch.

We're still waiting on a full block diagram disclosure from AMD, and when we do we'll update this news.

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  • abufrejoval - Sunday, May 26, 2019 - link

    If there was really flexible ways to bi/quad-furicate the 16 PCIe 4 lanes to what peripherals like 10Gbit Ethernet can actually handle, it could do wonders in workstation space.

    Wish it was as flexible as the base architecture of Inifinity Fabric actually seems to be, but don't know how OEMs could achieve that with the hard wires they need into the motherboards.
  • StevenD - Tuesday, May 28, 2019 - link

    Never understood the obsession with 10G. Unless you're moving VMs to other machines constantly or editing raw 4k over the network it's really overkill even for the enthusiast consumer.
    Your speed is 4GBps, until recently with NVME it was almost impossible to feed the network card.
  • bcronce - Tuesday, May 28, 2019 - link

    To properly schedule network traffic to minimize jitter and loss, you need about 25% more bandwidth than provisioned. If you expect to transfer up to 1Gb/s of traffic, you should really had 1.25Gb/s of bandwidth if you don't want networking hickups.

    I am less concerned with 10Gb than 2.5/5.0Gb, but those two new protocols are based on 10Gb, and pretty much everyone who makes nbase-t, supports 2.5/5/10. May as well just say "10".
  • Chaitanya - Monday, May 27, 2019 - link

    Is that "lightning" m.2 a pcie 4.0 based M.2 slot?
  • ArcadeEngineer - Monday, May 27, 2019 - link

    Yes, Matisse/X570 does 16 lane GPU+4 lanes direct CPU-connected M.2+4 lanes chipset.
  • blingon - Monday, May 27, 2019 - link

    "as will the four PCIe lanes assigned to the first NVMe M.2 slot"

    What if you use a PCIe SSD? Plus a GPU?
  • blingon - Monday, May 27, 2019 - link

    ...I guess this was just a description of a typical MB layout, let's hope there's some variety.
  • Death666Angel - Monday, May 27, 2019 - link

    What are you actually talking about?!
    The Ryzen 3000 CPUs provide 24 PCIe 4.0 lanes. 16 go to the GPU(s) in a 1x16 or 2x8 configuration dependant on the MoBo. Then there are 4 lanes to a dedicated M.2 NVME slot (which is a PCIe SSD) and 4 lanes to the X570 (and B550 etc.) chipset, which then further allocates lanes to SATA/USB/M.2(PCIe/SATA)/Controllers etc. dependant on the actual MoBo.
  • John_M - Monday, May 27, 2019 - link

    My question is, what generation of PCIe lanes come out of the X570 to feed the lower slots? With X370 and X470 it was PCIe 2.0 and the lower slots were starved of lanes. Does X570 give out PCIe 3.0, which means the number will be restricted and the bandwidth wasted, or does it give out twice as many PCIe 2.0 lanes? I hope it is the latter.
  • 12345 - Monday, May 27, 2019 - link

    Leaked block diagrams showed all the chipset lanes to slots are gen4 pcie. MSI also is using a pcie multiplexer on some boards. So both the top slots can get x16, what I wonder is if its smart enough to mux two x16 3.0 devices into a single x16 4.0 signal back to the cpu. Anyone know more about how pcie multiplexers work?

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