Synopsys, one of the leading developers of chip development tools and silicon IP, demonstrated its CXL over PCIe 5.0 as well as CCIX 1.1 over PCIe 5.0 solutions at ArmTechCon 2019. The showcase indicates that the company’s IP is up and running, and is ready to be licensed by interested parties. CXL and CCIX are chip-to-chip interconnect protocols for connecting processors to various accelerators that maintains memory and cache coherency at low latencies. Both protocols are designed for heterogeneous systems that use traditional CPUs along with accelerators featuring scalar, vector, matrix, and spatial architectures. Both CXL 1.0/1.1 as well as CCIX 1.1 use PCIe Gen 5 PHY stack at 32 GT/s per lane and support different link width natively. Aiming the same market segment and...
Xilinx Announces Project Everest: The 7nm FPGA SoC Hybrid
This week Xilinx is making public its latest internal project for the next era of specialized computing. The new product line, called Project Everest in the interim, is based...16 by Ian Cutress on 3/19/2018